1. Technical Field
The present invention generally relates to semiconductor layout design. More particularly, the present invention relates to pattern-based via redundancy insertion.
2. Background Information
With the ever decreasing size of semiconductors, wiring and wiring design becomes more and more complex, and manufacturing yields become increasingly challenging. To electrically connect various layers and/or devices (e.g., between transistors), vias are strategically placed. As one skilled in the art will know, the term VIA means Vertical Interconnect Access between wiring layers in semiconductor devices. VIAs are also sometimes referred to as “cuts.” Due to the importance of VIAs, and typical yield reductions as sizes decrease, it has become necessary to build in redundant VIAs, in case a given one becomes a casualty to the complex semiconductor manufacturing process. The process of designing redundant VIAs is known as Via Redundancy Insertion (VRI).
VRI is done both at the design phase, as well as post-design prior to manufacturing, and is typically driven by the analysis of design rules surrounding a given via in an existing layout. The analysis is performed with computer assistance, including, for example, Design Rule Check (DRC) engines. VIAs initially not redundant may be replaced with redundant VIAs by analysis of replacement candidates using one or more DRC engines. As the number of design rules increases with each reduction in size, the computations that must be performed by the DRC engines itself becomes a factor in VRI.
Therefore, a need continues to exist for improved VRI techniques.